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It takes an entire sequence of inputs to detect many of the possible faults in a sequential circuit. Sequential circuits can be tested by checking that such a circuit functions as specified by its state table [9, 10]. This is an exhaustive approach and is practical only for small sequential circuits. The approach may be summarized as follows: Given the state table of a sequential circuit, find an input/output sequence pair (X, Z) such that the response of the circuit to X will be Z if and only if the circuit is operating correctly.
13: Multiple backtracks along H−E−C and H−G−F−C. done via both H−E−C and H−G−F−C, the value at C can be set so that the value at H is justified. In PODEM, a logic value assigned to a primary input in order to achieve one objective may in turn result in the failure of satisfying another objective, thereby forcing a backtrack. 14. First, the value D is assigned to the line Z and the value 1 to each of the inputs M and N. The initial objectives are to set M and N to 1. By the multiple backtrack, G and I are assigned 1 (note that instead of G and I, L could be assigned logic 1).
215−22 (May 1981).  Fujiwara, H. and T. Shimono, “On the acceleration of test generation algorithms,” IEEE Trans. , 1137−44 (December 1983).  Park, E. and M. Mercer, “Robust and nonrobust tests for path delay faults in a combinational circuit,” Proc. Intl. , 1027−34 (1987).  Reddy, S. , C. Li, and S. Patil, “An automatic test pattern generator for the detection of path delay faults,” Proc. IEEE Intl. Conf. CAD, 284−7 (November 1987).  Schulz, M. , K. Fuchs, and F. Fink, “Advanced automatic test pattern generation techniques for path delay faults,” Proc.