By Varghese George
Low-Energy FPGAs: structure and Design is a chief source for either researchers and training engineers within the box of electronic circuit layout.
The ebook addresses the power intake of Field-Programmable Gate Arrays (FPGAs). FPGAs have gotten well known as embedded parts in computing structures. The programmability of the FPGA can be utilized to customise implementations of features on an software foundation. This ends up in functionality profits, and allows reuse of high-priced silicon.
bankruptcy 1 offers an summary of electronic circuit layout and FPGAs. bankruptcy 2 seems on the implication of deep-submicron know-how onFPGA strength dissipation. bankruptcy three describes the exploration atmosphere to steer and assessment layout judgements. bankruptcy four discusses the architectural optimization strategy to guage the trade-offs among the flexibleness of the structure, and the impression at the functionality metrics. bankruptcy five studies various circuit innovations to minimize the functionality overhead of a few of the dominant parts. bankruptcy 6 indicates how to configure FPGAs to lessen the programming overhead. bankruptcy 7 addresses the actual cognizance of a few of the serious parts and the ultimate implementation of a particular low-energy FPGA. bankruptcy eight compares the prototype array to an similar advertisement architecture.
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Additional info for Low-Energy FPGAs — Architecture and Design
A natural progression from these projects is the use of FPGAs as a principal component in mainstream products. A major hurdle is the high power consumption of existing FPGA architectures. The same features that make an FPGA desirable are also responsible for making it extremely expensive in terms of energy. For example, it will be shown in Chapter 2 that the power consumption of an XC4085 chip running at a system frequency of 50 MHz is approximately 6W. At present, the high power dissipation is a limiting factor in energy sensitive domains.
8, and is similar to that given in [Alexander94] [Kahng95]. The target architecture description, placement of logic blocks, and connectivity of logic blocks are the inputs to the tool. Since the routing is sequential in nature, the nets are ordered to improve the chances of successful routing. The core of the tool is a GSMT algorithm [Alexander96], which attempts to route the net on the target graph. If not all of the nets can be routed, the nets are reordered, and another pass is made. Upon successful routing, the information regarding the routes for all of the nets is available for further analysis.
The reliability of an integrated circuit degrades as an exponential function of the junction temperature. The main purpose of packaging and thermal control is to maintain the junction temperature within the functional and maximum allowable limits while maintaining acceptable circuit reliability. The functional limit defines the temperature at which the performance specifications can be met. The maximum limit is the temperature to which the device can be safely exposed without causing irreversible changes in operating characteristics.